Is there a way to run the USB3 super speed at a lower rate (e.g 1Gbs) instead of 5Gbs. The reason is the new usb3 host design will be tested in an FPGA, but the FPGA is not capable of exceeding 1Gbs. Are there any device peripherals that would be able to talk to such a host ?
Using HS (480 mbs) wouldn't work since the intent is to test the usb3 protocol. Or alternatively if the usb3 SS host protocol can be run on the 480 Mbs rate would any peripheral beable to interoperate with that ?
why not consider using an external PHY like the TI TUSB1310A. The PIPE interface is 16 bits running at 250Mhz. You can easily convert that to a 32 bits internal bus and have most of the logic running at 125Mhz.